This invention relates generally to integrated circuits and more particularly to a structure and process for contacting and interconnecting semiconductor devices within an integrated circuit. An integrated circuit comprises an ensemble of semiconductor devices. The semiconductor devices are principally formed in a single-crystal semiconductor wafer. A thin dielectric layer either grown on or deposited on the wafer surface and regions of polycrystalline semiconductor material deposited on the thin dielectric layer are integral parts of many semiconductor devices. A relatively thick dielectric layer is deposited over the semiconductor devices, and contact openings are etched through this dielectric layer to provide access to terminals of the semiconductor devices. The ensemble of semiconductor devices is interconnected (integrated) by a complex pattern of metal lines running on top of the thick dielectric layer. The lines contact terminals of the semiconductor devices through the openings in the dielectric layer. A protective coating is applied after formation of the interconnect pattern. Openings are made through the protective coating to provide access to square features of the interconnect pattern called bond pads. Electrical connections to the integrated circuit are made at the bond pads. A very-large-scale integrated (VLSI) circuit may contain over one million semiconductor devices, include several meters of interconnect line length, and have more than one hundred bond pads placed around the circuit perimeter.
Today, most integrated circuits are manufactured using silicon wafers, and an aluminum alloy is almost always used to interconnect the silicon semiconductor devices. A low concentration (typically, 1 percent) of silicon is incorporated in the aluminum alloy to prevent excessive absorption of silicon from terminal regions of the semiconductor devices. A low concentration (typically, 0.5 to 4 percent) of a metal such as copper is often incorporated in the aluminum alloy to improve its mechanical stability.
When the density of semiconductor devices in VLSI circuits became great enough to require that interconnect line widths be decreased to less than about 2 micrometers, aluminum alloys of uniform composition became inadequate as a material for the lines. At such narrow line widths, current densities in VLSI circuits can be in the range of 1 million amperes per square centimeter. At current densities on the order of 1 million amperes per square centimeter, the rate of electron interactions with aluminum ions is sufficient to cause migration (electromigration) of aluminum in the direction of the electron flow. Electromigration of aluminum causes integrated circuits to fail due to the formation of voids (open circuits) in the interconnect lines. See J. R. Black, "Physics of Electromigration", Proceedings of 12th Reliability Physics Symposium, pp 142-149, 1974 and J. G. J. Chern, W. G. Oldham, and N. Cheung, "Electromigration in Al/Si Contacts-Induced Open-Circuit Failures", IEEE Transactions on Electron Devices, Vol ED-33, pp 1256-1262, 1986. Interactions between the electron stream and silicon at contacts to semiconductor device terminals can also cause circuit failures due to extraction of silicon from the terminals. See J. G. J. Chern, W. G. Oldham, and N. Cheung, "Contact-Electromigration-Induced Leakage Failure in Aluminum-Silicon to Silicon Contacts", IEEE Transactions on Electron Devices, Vol. ED-32, pp 1341-1346, 1985. Because the thermal expansion coefficients of aluminum alloys and silicon do not match, thermal cycles used in integrated circuit manufacturing cause stresses which exceed the yield strength of narrow interconnect lines. See P. A. Flinn, D. S. Gardner, and W. D. Nix, "Measurement and Interpretation of Stress in Aluminum-Based Metallization as a Function of Thermal History", IEEE Transactions on Electron Devices, Vol. ED-34, pp 689-699, 1987. When the lines yield, circuits fail due to formation of aluminum voids. See J. W. McPherson and C. F. Dunn, "A Model for Stress-Induced Metal Notching and Voiding in Very-Large-Scale Integrated Al-Si (1%) Metallization", Journal of Vacuum Science and Technology, Vol. B5, pp 1321-1325, 1987.
Structures of alternating layers of an aluminum alloy and a refractory metal have been proposed as a material for narrow-width interconnect lines. See D. S. Gardner, T. L. Michalka, K. C. Saraswat, T. W. Barbee, J. P. McVitte, and J. D. Meindl, "Layered and Homogeneous Films of Aluminum and Aluminum/Silicon with Titanium and Tungsten for Multilevel Interconnects", IEEE Transactions on Electron Devices, Vol. ED-32, pp 174-183, 1985. These layered material structures are able to sustain much higher current densities than aluminum alloys of uniform composition. These layered structures are also mechanically much stronger than uniform alloys; therefore, the layered structures are able to survive more severe thermal cycles than uniform alloys.
Although material structures comprised of aluminum alloy layers and refractory metal layers offer improvements over uniform alloys, the refractory metal layers can cause severe problems. After initial formation of the structure, aluminum alloy layers and refractory metal layers react, and properties of the interconnect lines degrade as a consequence of the metallurgic reactions. When semiconductor device terminals are contacted directly by lines made of these layered materials, silicon is extracted from the device terminals to such an extent that circuits fail. See K. Hinode, N. Owada, T. Terada and S. Iwata, "Silicon Take-Up by Aluminum Layered with Refractory Metals", IEEE Transactions on Electron Devices, Vol ED-34, pp 700-705, 1987 and R. E. Jones and L. D. Smith, "Contact Spiking and Electromigration Passivation Cracking Observed for Titanium Layered Aluminum Metallization", Proceeding of the IEEE VLSI Multilevel Interconnect Conference, 1985. A barrier must, therefore, be interposed between the interconnect line and the terminal of the semiconductor device to prevent silicon extraction if layered structures are used for interconnect lines in VLSI circuits.
A metallurgic barrier can be produced by depositing titanium nitride (TiN) over the device terminals, but semiconductor device characteristics may be degraded. TiN films can be formed by reactive sputtering of titanium in a nitrogen atmosphere, but the as-deposited films exhibit compressive stresses at sufficient levels to cause cracking and peeling of the films during thermal cycles subsequent to film deposition. See I. Suni, M. Maenpaa, and M. A. Nicolet, "Thermal Stability of Hafnium and Titanium Nitride Diffusion Barriers in Multilayer Contacts to Silicon", Journal of the Electrochemical Society, 130 No. 5, pp 1215-1218, 1983. Incorporation of oxygen in the TiN can be used to reduce compressive stress in the films, but incorporation of oxygen in sufficient concentrations to reduce stress results in a significant increase in the electrical resistance of the TiN film. See S. S. Ang, "Titanium Nitride Films with High Oxygen Concentration", Journal of Electronic Materials, Vol. 17 No. 2, pp 95-100, 1988. Also, because a thin (10 to 20 Angstroms) layer of silicon oxide rapidly forms on exposed silicon surfaces, it is unlikely that TiN films, especially TiN films which incorporate oxygen, can form reliable, low-resistance contacts to silicon semiconductor terminals. The combined resistance of the TiN film and TiN-silicon interface is in series with a semiconductor device terminal and will cause degradation in the characteristics of the semiconductor device.
A two-step process has been described for forming low-resistance electrical contacts to semiconductor device terminals and metallurgic barriers over the terminals. See P. J. Rosser and G. J. Tomkins, "Self Aligned Nitridation of TiSi.sub.2 : A TiN/TiSi.sub.2 Contact Structure," Material Research Society Symposium Proceedings, 1985. Titanium is deposited on the semiconductor wafer, preferably using a sputtering process. The titanium is reacted with silicon and nitrogen during first thermal cycle to form a rather thick layer of titanium disilicide within the surface region of the semiconductor device terminals and a rather thin layer of titanium oxynitride over the surface of the device terminals. Because impurities tend to segregate into the oxynitride layer and because unreacted titanium may remain after the first thermal cycle, the titanium oxynitride layer and any residual titanium are then removed by etching with a suitable chemical solution. A portion of the titanium disilicide (TiSi.sub.2) is converted to titanium nitride (TiN) during a second thermal cycle in a nitrogen atmosphere. The final structure at the device terminals is a TiSi.sub.2 layer to provide an electrical contact and an overlying TiN layer to provide a metallurgic barrier.
Although it produces a low-resistance electrical contact and a metallurgic barrier, the above-described process has inherent disadvantages. During the first thermal cycle too much silicon is consumed from the device terminals, because a rather thick layer of TiSi.sub.2 must be formed. Control of the TiSi.sub.2 and TiN thicknesses is very difficult, because reactions proceed rapidly at the temperature required to form TiSi.sub.2 and the thicknesses are controlled by the duration of the thermal cycle. Finally, the above-described process is rather complex and difficult to apply in volume manufacturing.
A good metallurgic barrier and a low-resistance electrical contact can be simultaneously formed. See E. H. Stevens, P. J. McClure and C. W. Hill, "Semiconductor Contact Process," U.S. patent Ser. No. 4,784,973. First, a very thin (10 to 20 Angstroms) control layer of silicon oxide or silicon oxynitride is grown over the silicon surfaces that are exposed at contact openings to terminals of semiconductor devices. Then, a layer of titanium (Ti) is deposited under high vacuum conditions. Next, the titanium is reacted with nitrogen or ammonia at a temperature of 600 degrees to 700 degrees centigrade to simultaneously form a thin (0.05 to 0.1 micrometers) layer of titanium disilicide (TiSi.sub.2) within the silicon and layer of TiN of 0.05 to 0.2 micrometers thickness over the silicon. The control layer of silicon oxide or silicon oxynitride allows the relative thicknesses of the TiN and TiSi.sub.2 to be controlled. The control layer also supplies small amounts of oxygen and nitrogen for incorporation in the TiN film. The TiSi.sub.2 layer forms a reliable, low-resistance electrical contact between silicon and TiN. The TiN layer with trace amounts of oxygen and excess nitrogen incorporated in its grain boundaries provides a reliable metallurgic barrier which has an acceptable value for electrical resistance. These simultaneously-formed barriers and contacts were improvements over previous approaches, and were successfully used in conjunction with interconnect lines made of aluminum alloys layered with refractory metals to manufacture VLSI memory circuits.
The method described above ca be used to simultaneously produce good metallurgic barriers and good electrical contacts between the barriers and silicon at semiconductor device terminals, but the method is somewhat difficult and expensive to apply in volume manufacturing of VLSI circuits. Growth of very thin control layers with predictable properties is difficult. Because the titanium layer must be deposited under high vacuum conditions to prevent incorporation of too much oxygen, expensive vacuum deposition equipment is required, and the interior of the equipment must be kept extremely clean. During the reaction of titanium in a furnace to form the TiN and TiSi.sub.2 layers, oxygen and other trace contaminants must be held to low concentration levels. Thus, furnace maintenance must be done thoroughly and frequently.
Although simultaneously-formed TiN layers for metallurgic barriers and TiSi.sub.2 layers for contacts between TiN and silicon allow the use of layered material structures for VLSI circuit interconnect lines, the layered material structure of the interconnect lines can still cause reductions in VLSI circuit performance and reliability. To sufficiently increase the current-carrying capacity and mechanical strength of narrow interconnect lines, thicknesses of the refractory metal layers must be in the range of 0.02 to 0.05 micrometers. During thermal cycles subsequent to deposition of the layered material structure, the refractory metal layers react with aluminum to form compounds which exhibit high electrical resistivities. Hence, resistances of interconnect lines made of layered structures can be significantly higher than resistances of lines made of uniform aluminum alloys. The consequence of increased interconnect line resistances is reduced VLSI circuit performance. Aluminum can react with TiN and after sufficient time the TiN barriers may develop imperfections. See M. Wittmer, "Interfacial Reactions Between Aluminum and Transition-Metal Nitride and Carbide Films", Journal of Applied Physics, Vol. 53, No. 2, pp 1007-1012, 1982. Because aluminum-refractory metal compounds absorb silicon to high concentrations silicon will be extracted from a terminal of a semiconductor device and absorbed in the intermetal compounds if even the slightest imperfection develops in a TiN barrier.
The coating applied over the integrated circuit cannot be expected to provide both mechanical support for the interconnect pattern and protection for the underlying circuit. At completion of circuit manufacturing, the coating is often in a state of compressive stress; consequently, because it is in direct contact with the interconnect pattern, the coating transmits a tensile stress to the interconnect lines and weakens the lines. If special care is taken to form the coating in a state of high tensile stress, the interconnect lines are strengthened, but the high tensile stress can cause the coating to crack and as a consequence, fail to protect the integrated circuit.
If interconnect lines are made using a mechanically strong layered material structure and if the lines are additionally strengthened by applying a protective coating in a state of moderate tensile stress, reliable VLSI circuits can be manufactured.
Electrical connections to integrated circuits ar made at bond pads which are usually placed around the circuit chip perimeter. The most commonly used means of establishing electrical connections is a thermocompression bond between the bond pad and a small diameter gold or aluminum alloy wire. Recently, there has been a trend to establish electrical connections by soldering the chips to a conductor pattern on a suitable substrate or by attaching one end of metal alloy tabs to the integrated circuit bond pads and subsequently attaching the other end of the tabs to a conductor pattern on a substrate. See P. Singer, "Multi-chip Packaging on Silicon Substrates," Semiconductor International, p 34, June, 1987, and R. Bowlby, "The DIP May Take its Final Bows," IEEE Specturm, pp 37-42, June, 1985.
In addition to having sufficient mechanical strength and low electrical resistance, the interconnect material structure must be compatible with the means employed to make electrical contacts to the integrated circuit. If thermocompression bonding of gold wires is employed, the uppermost layer of the material structure cannot be a refractory metal unless a layer of appropriate material is added over the bond pads. If either soldering to conductor patterns on a substrate or attachment of metal tabs is employed, the uppermost layer of the interconnect material structure must either be a metallurgic barrier or a barrier layer must be added over the bond pads.
Bond pads occupy significant area on the surface of VLSI circuits. Severe deformations of the bond pad materials are produced during the thermocompression bonding of wires to the pads. In the prior art, semiconductor devices are not placed beneath bond pads in high reliability circuits, because the deformations produced during bonding can be transmitted to the underlying devices and thereby damage those devices. If semiconductor devices could be placed beneath bond pads, areas and manufacturing costs of VLSI circuits would be reduced and performances of VLSI circuits would be increased.
In view of the foregoing background it can be seen that there is a need in the art for an improved material structure for use in contacting and interconnecting semiconductor devices within VLSI circuits and a process which is amenable to volume manufacturing for forming the improved material structure.